Minutes, IBIS Quality Committee 17 Mar 2009 11-12 AM EST (8-9 AM PST) ROLL CALL Adam Tambone Anders Ekholm, Ericsson Barry Katz, SiSoft Benny Lazer Benjamin P Silva Bob Cox, Micron * Bob Ross, Teraspeed Consulting Group Brian Arsenault * David Banas, Xilinx * Eckhard Lenski, Nokia Siemens Networks Eric Brock * Guan Tao, Huawei Technologies Gregory R Edlund Hazem Hegazy Huang Chunxing, Huawei Technologies John Figueroa John Angulo, Mentor Graphics Katja Koller, Nokia Siemens Networks Kevin Fisher Kim Helliwell, LSI Logic Lance Wang, IOMethodology Lynne Green * Mike LaBonte, Cisco Systems Mike Mayer, SiSoft * Moshiul Haque, Micron Technology Muniswarareddy Vorugu, ARM Ltd * Pavani Jella, TI Peter LaFlamme Randy Wolff, Micron Technology Radovan Vuletic, Qimonda Robert Haller, Enterasys Roy Leventhal, Leventhal Design & Communications Sherif Hammad, Mentor Graphics Todd Westerhoff, SiSoft Tom Dagostino, Teraspeed Consulting Group Kazuyoshi Shoji, Hitachi Sadahiro Nonoyama Liqun, Huawei Everyone in attendance marked by * NOTE: "AR" = Action Required. -----------------------MINUTES --------------------------- Mike LaBonte conducted the meeting. Call for patent disclosure: - No one declared a patent. AR Review: - Mike post updated IQ specification document - Done - Section 6 - markup sent - section 6.5 - Mike look into MeetingPlace issues - Bob need several tries for web sharing - Waiting for WebEx provisioning to be completed. - Mike propose IBISCHK bug for 5.5.6 - TBD New items: Continued review of the IQ specification: 6.5. {LEVEL 3} Differential models contain appropriate waveform tables - Bob: LVDS silicon is skewed out of it's normal range with [Ramp] fixtures - The [Ramp] fixtures do not match waveform fixtures - Sometimes different fixture voltages give good results - Mike: Is [Ramp] measured the same way for differential buffers? - Bob: The differential buffer in IBIS is a pair of single ended buffers - Mike: Are there right and wrong ways to do LVDS [Ramp]? - We added a sentence to 5.4.1 to require waveforms for LVDS, etc. - We marked 6.5 to be deleted - Now Section 6 really is completely deleted David showed the presentation 'IBIS-to-Spice Correlation': - This was by David and Roy for an IBIS summit - http://www.vhdl.org/pub/ibis/summits/jun07/banas.pdf - Brief history of the IBIS Accuracy Handbook - It was the first attempt at quantitative characterization - Customers complained about IBIS accuracy - The Model Correlation committee was formed in 2007 - Mostly Roy Leventhal and David - Guan Tao also contributed - A new "5 metrics" approach was recommended - The Curve Overlay approach used in the handbook was a good first step - Specific features give model makers insight into quality - The IBIS Accuracy Handbook hints at this in the last pages - 5 Metrics: - Settling high level error - Settling low level error - Rise time error - Fall time error - Duty cycle error - Xilinx ran a test using thresholds from 5% to 10% - It showed no high level, low level, or duty cycle errors - Rise time and fall time errors go up with lower thresholds - Moshiul: The error threshold is a maximum limit? - Yes - 21 I/O standards * 3 PVT corners = 63 tests - Mike: A scattergram view might be interesting - One theory is that IBIS drivers may be weaker than Spice - This was not supported by the evidence - Another theory is that linear interpolation of V/T may introduce errors - Low V/T point density can result in slower apparent slew rates - Mike: A point interval equal to rise time is a pathological case - David: Less exaggerated cases still introduce error - Correlation checking has to be automated - It greatly reduces human effort - Mike: Can we ignore differences in overshoot levels? - This has been suggested - These metrics will be added - Bob: It really helps to show waveforms in these quality reports Slide: Comparison of IBIS vs. Spice and IBIS vs. Bench - We tend to report magnitudes of discrepancies for IBIS vs. Spice - What we want is for IBIS to adequately "window" the bench measurements - The range produce by IBIS must lie within that produced by SPICE - We measure the margins remaining - A positive margin is required Example of Xilinx automated report: - 100 parts bench measured - Problem spots are highlighted in red - Margins are given in a table Next meeting: 24 Mar 2009 11-12 AM EST (8-9 AM PST) Meeting ended at 12:04 PM Eastern Time.